1. Field of the Invention
The present invention relates to a parallel AD converter and, more particularly, to a parallel interpolation AD converter in which an usage of an interpolation technique avoids an increase in circuit size and also enables high-speed operation at low electric power consumption.
2. Description of Related Art
FIG. 8 shows a basic configuration of the parallel AD converter. This parallel AD converter is basically provided with a sample/hold (S/H) circuit 101, a reference voltage generation circuit 102, a comparator array 103 and an encoding circuit 104. The sample/hold circuit 101 samples an input analog signal and holds its sampled value for a certain period. The reference voltage generation circuit 102 is configured such that resistors R are connected in series, and it generates a plurality of reference voltages, in which voltage values are different, at respective connection nodes of the resistors R.
The comparator array 103 is configured such that comparators whose number corresponds to their resolution capability are arranged in the array, and it compares a hold voltage of the sample/hold circuit 101 with the plurality of reference voltages generated by the reference voltage generation circuit 102 all at once. At this time, among the respective comparators of the comparator array 103, when the closest reference voltage to the hold voltage is defined as the boundary voltage, all the comparators whose reference voltages are equal to or higher than the hold voltage output a logic xe2x80x9c0xe2x80x9d level, and all the comparators whose reference voltages are lower than the hold voltage output a logic xe2x80x9c1xe2x80x9d level.
By the way, although not shown; a logic processor circuit is usually installed at a later stage of the comparator array 103. This, logic processor circuit carries out a logic process for carrying out an exclusive-OR between the outputs of the comparators adjacent to each other, in the comparator array 103. The encoding circuit 104 encodes the result of the logic process in the logic processor circuit, and digitally converts it, and obtains a digital signal.
Here, in each comparator in the comparator array 103, a sufficient gain can not be usually obtained from an amplifying stage composed of a single stage. Thus, as shown in FIG. 8, an amplifying stage composed of about two stages is installed, and, in many cases a latch circuit is installed at a final stage. Hence, for example, in a case of six bits, 63 pieces of first pre-amplifiers, 63 pieces of second pre-amplifiers and 63 pieces of latching circuits are respectively required.
In the case of the above-mentioned basic parallel AD converter, it is constituted by the comparators corresponding to the resolution capability of the comparator array 103. Thus, as the resolution capability is improved, the circuit size is exponentially expanded. In association with this expansion, the electric power consumption is increased, and the chip size is also enlarged.
On the contrary, a parallel interpolation AD converter in which an usage of an interpolation technique protects an expansion in a circuit size and also enables a high-speed operation at low electric power consumption is reported in the following document:
Document: [A Dual-Mode 700 Msps 6 bit 200 Msps 7 bit ADC in a 0.25 xcexcm Digital CMOS] (IEEE Journal of Solid-State Circuits, Vol.35, No.12. December 2000).
FIG. 9 shows the configuration of the parallel interpolation AD converter. This parallel interpolation AD converter is provided with a sample/hold circuit 111, a reference voltage generation circuit 112, a first preamplifier array 113, a second pre-amplifier array 114, a latching circuit array 115 and an encoding circuit 116. The basic operation for AD conversion is similar to the case of the above-mentioned basic parallel AD converter.
However, in this parallel interpolation AD converter, the number of the pre-amplifiers in the first preamplifier array 113 is reduced to one-half thereof, and on the other hand, the second pre-amplifier array 114 generates an interpolation signal from the outputs of two pre-amplifiers adjacent to each other in the first preamplifier array 113 and obtains the comparator output corresponding to the resolution capability. In this way, the second-pre-amplifier array 114 generates a reduced comparator output through the interpolation. Thus, the number of the pre-amplifiers in the first pre-amplifier array 113 can be reduced to one-half thereof. Hence, this is the approach that is effective for the miniaturization of circuit size and the reduction in electric power consumption.
However, the parallel interpolation AD-converter according to the-above-mentioned conventional example has the following problem in the circuit implement. That is, if the first pre-amplifier array 113 uses a transistor of a small size in designing a circuit, the property of the transistor is liable to be varied. In association with the variation, an offset is brought about. Thus, in order to cancel this offset, a chopper-type amplifier is used as each pre-amplifier.
As mentioned above, if the chopper-type amplifier is used as each pre-amplifier in the first pre-amplifier array 113, a capacitor C to detect a difference between a reference voltage and a hold voltage of the sample/hold circuit 111 interposes between an output end of the sample/hold circuit 111 and an input end of each preamplifier. This results in a tendency to increase the input capacitance of the first pre-amplifier array 113, although the number of the amplifiers in the first pre-amplifier array 113 is halved.
This input capacitance becomes a heavy load on the sample/hold circuit 111. For this reason, the sample/hold circuit 111 requires a circuit configuration containing an output stage having a sufficient driving performance. The configuration in which the output stage has a sufficient driving performance implies that the electric power consumption in the sample/hold circuit 111 is large. Thus, irrespective of the parallel interpolation AD converter that is expected to be the approach that is effective for the reduction in the electric power consumption, there is brought about the increase in the electric power consumption of the entire complementary parallel-type AD converter, consequently.
The present invention is proposed in view of the above-mentioned problems. Accordingly, there is a need to provide a parallel AD converter which enables an assured reduction in electric power consumption and also enables a faster circuit operation.
In order to solve the above-mentioned subject, the present invention provides a parallel interpolation AD converter, which comprises a reference voltage generator, a first amplifier array and a second amplifier array. The voltage generator generates a plurality of reference voltages. The first amplifier array is constituted by arranging first differential amplifier circuits, in which an analog signal is inputted to a comparison input end of each of the first differential amplifiers, and a corresponding reference voltage among the plurality of reference voltages is inputted to a reference input end of each of the first differential amplifier circuits, respectively, and each of the first-differential amplifier circuits amplifies a potential difference between both input ends. The second amplifier array comprises interpolation amplifier circuits, each of which interpolates and amplifies a portion between output voltages from the first differential amplifier circuits adjacent to each other in this first amplifier array, and second differential amplifiers, each of which amplifies the output voltage from every other first differential amplifier in the first amplifier array. The interpolation amplifier circuits and the second differential amplifier circuits are alternately arranged. In the AD converter, the first differential amplifier circuit has a reset switch that is controlled so as to be opened or closed by a control clock of a predetermined cycle between the comparison input end and the reference input end. Each of the interpolation amplifier and the second differential amplifier circuit includes: a load transistor, a switching unit for selectively diode-connecting the load transistor in synchronization with the control clock; and a capacitor for keeping a voltage of the load transistor when the load transistor is diode-connected.
In the parallel interpolation AD converter having the above-mentioned configuration, each first differential amplifier in the first amplifier array has a reset mode-and an amplification mode. The comparison input end and the reference input end are short-circuited by the switch that is turned on (closed) at a time of the reset mode. Each first differential amplifier circuit, when proceeding to the amplification mode, amplifies the potential difference between the comparison input end and the reference input end and outputs it as a differential voltage. In each of the interpolation amplifier circuit and the second differential amplifier circuit in the second amplifier array, the load transistor is diode-connected (at a diode load) by the switching unit that is turned on at a time of the reset mode. Then, a voltage (corresponding to an offset) at the time of this diode load is accumulated in the capacitor. At a time of the amplification mode, the switching unit is turned off, and the load transistor is set at the original connection state. In accordance with the connection state of the load transistor switched by this switching unit, the gain of the amplifier is changed between the reset mode and the amplification mode. Thus, the offset occurring in the first differential amplifier circuit is suppressed by the compression effect of using this gain difference.